Speaker Details

Ananth Narayan is a senior software research engineer at Intel working on architectural aspects of composable infrastructure - Intel(R)  Rack Scale Design. He is the Lead Pathfinding Engineer in the Intel Rack Scale Design (RSD) team, focusing on platform pathfinding for the disaggregated composable hardware architectures, including storage, telemetry, workload fingerprinting using ML. His work within Intel RSD has spanned from PoCs on workload fingerprinting, dynamic creation of underlay networks, telemetry agents, orchestration & scheduling with OpenStack, and he has led the development of successful company demos at previous OpenStack Summits at Vancouver, Tokyo, Austin, and Barcelona.

He  is a project core for the OpenStack Valence project which provides support for hardware life cycle management of disaggregated resources within OpenStack.